Kumar, Satish and Sharma, B.K. and Sharma, Parkhi and Shamshi, M.A. (2009) 24 bit seismic processor for analyzing extra large dynamic range signals for early warning. Journal of Scientific & Industrial Research, 68 (5). pp. 372-378. ISSN 0022-4456
|
PDF
24 bit seismic processor for analyzing.pdf Download (154Kb) | Preview |
Abstract
Modified design is presented of existing 24 bit seismic data recorder comprising PC –architecture using PCI bus, ISA bus, and PC 104 bus in a single module to develop a flexible measurement set up. Paper elaborates use of building blocks [Disk on chip (DoC), GPS based timing unit, signal-processing module, and efficient software packages] worked out in visual C++ to develop compact sized instrument for quick decision-making with minimum error detection of true events. Paper describes Ethernet connectivity use for data downloading in a laptop without interruption of event data acquisition. Software packages for conversion of recorded data into SUDS and SEISAN formats have been realized and incorporated.
Item Type: | Article |
---|---|
Uncontrolled Keywords: | 24 Bit seismic processor; Digital seismograph; Early warning; Earthquake; Seismic Alert System |
Subjects: | CSIO > Strategic Instrumentation |
Depositing User: | Ms. J Shrivastav |
Date Deposited: | 30 Mar 2012 11:09 |
Last Modified: | 30 Mar 2012 11:09 |
URI: | http://csioir.csio.res.in/id/eprint/241 |
Actions (login required)
View Item |